On Wed, 02 Jun 2004 10:37:28 GMT,Rick T
penned this whopper in microsoft.public.windowsme.hardware

B.J.Honeycut wrote:

On Tue, 01 Jun 2004 12:10:03 GMT,Rick T
penned this whopper in microsoft.public.windowsme.hardware


Richard G. Harper wrote:

'tis true. Most memory manufacturers are warning about this. A
quick Google should give you the details.


hmm... the reason seems to be that the SPD timings might be
different... but that's really a BIOS issue more than anything
else... also SDRAM produced as 66/100 is generally 5V as opposed to
100/133 @ 3.3V. Learn something new every day.



Rick



Watch out for latency timing too: CL3, CL2.5 or CL2.0, they don't mix
in the same system and require BIOS adjustments if even supported.
RTFM to be sure.


Well I"m mixing CL3 and "CL2.5" semi-successfully (I'm only getting
CL3)

Rick


A lot of boards fall back to the lowest stting available. That wasn't true
until recently, and shouldn't be relied on, considering the extra expense
you pay for and get no use from. JMH accounting O.

--
"Time will bring to light whatever is hidden;
it will cover up and conceal what is now shining in splendor."
Horace (65 - 8 BC); Roman poet.

Mike